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Posting history for user ISEQ::COFFEY

10 notes across 2 conferences

Summary of Posts

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Conference	Total Posts	Conference Title
marvin::vhdl	6	VHDL
ecadsr::verilog_vhdl	4	verilog

Conference ecadsr::verilog_vhdl (verilog)

4 posts

TOPIC	13.0	System Simulation using VHDL
	13.1	`Tue Nov 03 1992 04:07`	Try the Synopsys demo's.	9 lines
	13.5	`Tue Jan 19 1993 06:02`	I'll second that.	8 lines
TOPIC	15.0	`Thu Feb 11 1993 16:22`	Synopsys notes file?	4 lines
	15.2	`Fri Mar 26 1993 11:06`	Well.. almost!	15 lines

Conference marvin::vhdl (VHDL)

6 posts

TOPIC	79.0	`Thu Dec 17 1992 22:04`	ANy EISA models out there?	8 lines
TOPIC	80.0	`Thu Feb 11 1993 21:22`	Synopsys interest?	3 lines
TOPIC	83.0	? Ontario VHDL ?
	83.2	`Fri Apr 23 1993 09:58`	I thought leapfrog was Cadence.	9 lines
TOPIC	85.0	`Wed Apr 28 1993 09:02`	Structural ASIC simulation.	7 lines
	85.2	`Thu Apr 29 1993 13:20`	Why should pre-layout be any faster?	41 lines
	85.5	`Fri Apr 30 1993 14:03`	We have done some static analysis	47 lines

Additional information

First Post:	`Tue Nov 03 1992`
Last Post:	`Fri Apr 30 1993`
# Topics:	4
# Replies:	6
# We have note bodies for:	0

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